Università di Verona

In fully CMOS digital integrated systems, switching activity of logic gates is the source of the socalled “digital noise”. Together with interconnections parasitics, digital switching noise is known to cause “bouncing” effects, i.e. oscillations of on-chip supply and bias voltages, which can remarkably degrade overall system performance. Digital switching is a completely deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a digital integrated system makes digital switching a cognitively stochastic process. Therefore, logic transition activity can be analyzed using a stochastic approach. In particular, we model the digital switching current as a stationary shot noise process, and we derive both its amplitude distribution and its power spectral density. The goal of this work is a comparison between two different logic synthesis techniques: the same logic function is synthesized in classical SOP (Sum Of Products) and XOR-based circuits. In particular, we want to investigate if the use of XOR gates in the circuit reduces the digital switching noise. Simulation results shows that the circuit synthesized with XOR gates exhibits lower switching activity Ore 11.30: A. Bernasconi 1 , V. Ciriani 2 , R. Cordone 2 ( 1 Università di Pisa – 2 Università degli Studi di Milano) “Fully Testable kEP-SOP Networks” Abstract: Multi-level logic synthesis yields much more compact expressions of a given Boolean function with respect to standard two-level sum of products (SOP) forms. On the other hand, minimizing an expression with more than two-levels can take a large time. We introduce a novel algebraic four-level expression, named k-EXOR-projected sum of products (kEP-SOP) form, whose synthesis can be performed in polynomial time with an approximation algorithm starting from a minimal SOP. Our experiments show that the resulting networks can be obtained in very short computational time and often exhibit a high quality. We also study the testability of these networks under the Stuck-at-fault model, and show how fully testable circuits can be generated from them by adding at most a constant number of multiplexer gates. Multi-level logic synthesis yields much more compact expressions of a given Boolean function with respect to standard two-level sum of products (SOP) forms. On the other hand, minimizing an expression with more than two-levels can take a large time. We introduce a novel algebraic four-level expression, named k-EXOR-projected sum of products (kEP-SOP) form, whose synthesis can be performed in polynomial time with an approximation algorithm starting from a minimal SOP. Our experiments show that the resulting networks can be obtained in very short computational time and often exhibit a high quality. We also study the testability of these networks under the Stuck-at-fault model, and show how fully testable circuits can be generated from them by adding at most a constant number of multiplexer gates. Ore 12.00: A. Rosiello 1 , F.Ferrandi 1 , D. Pandini 2 , D. Sciuto 1 ( 1 Politecnico di Milano – 2 ST Microelectronics) “A hash-based approach to extract functional regularity during logic synthesis” Abstract: Performance, power and functionality, yield and manifacturability are rapidly becoming additional critical factors that must be considered at higher levels of abstraction. A possible solution to improve yield e manifacturability is based on the detection of regularity at logic level. This lecture focuses its attention on regularity extraction after technology independent logic synthesis, to detect recurring functionalities during logic synthesis and thus constraining the physical design phase to exploit the regular netlist produced. A fast heuristic to the template identification is proposed and analyzed on a standard set of benchmarks both sequential and combinational. Performance, power and functionality, yield and manifacturability are rapidly becoming additional critical factors that must be considered at higher levels of abstraction. A possible solution to improve yield e manifacturability is based on the detection of regularity at logic level. This lecture focuses its attention on regularity extraction after technology independent logic synthesis, to detect recurring functionalities during logic synthesis and thus constraining the physical design phase to exploit the regular netlist produced. A fast heuristic to the template identification is proposed and analyzed on a standard set of benchmarks both sequential and combinational. Ore 12.30: N. Bombieri (Università di Verona) “A TLM Design-for-Verification Methodology” Abstract:. Transaction Level Modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration. It allows designers to focus on design functionality, while abstracting away implementation details that will be added at lower abstraction levels. However, its introduction gives rise to new challenges for designers and verification engineers, since design methodologies are not mature enough to automate every refinement step of the TLM-based design flow. Thus moving from transaction level to Register Transfer Level (RTL) requires manual interventions that may waste time and introduce design errors. In this context, we present a set of contributions aiming at (i) simplifying the design flow by automating some steps of the refinement process and (ii) combining static and dynamic techniques for improving the verification quality.. Transaction Level Modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration. It allows designers to focus on design functionality, while abstracting away implementation details that will be added at lower abstraction levels. However, its introduction gives rise to new challenges for designers and verification engineers, since design methodologies are not mature enough to automate every refinement step of the TLM-based design flow. Thus moving from transaction level to Register Transfer Level (RTL) requires manual interventions that may waste time and introduce design errors. In this context, we present a set of contributions aiming at (i) simplifying the design flow by automating some steps of the refinement process and (ii) combining static and dynamic techniques for improving the verification quality. Ore 13.30: Pranzo Pomeriggio Aula I Ore 14.30: Tavola rotonda sul tema “La sintesi logica: nuove prospettive e direzioni di ricerca” Ore 16.00 Davide Quaglia (Università Verona) “Networked Embedded Systems: Design Challenges” Abstract: Il seminario ha come oggetto la progettazione di applicazioni complesse basate su sistemi embedded di rete. Questo ambito e' oggetto di una straordinaria attenzione da parte della comunita' scientifica e del mondo industriale perche' promette di rivoluzionare il modo di costruire reti di telecomunicazioni e di realizzare la cosiddetta "ambient intelligence". Gli aspetti caratterizzanti delle reti di sistemi embedded sono: 1) presenza di un grande numero di nodi, 2) collaborazione tra i nodi al fine di raggiungere un obiettivo comune indipendente dal singolo nodo (ad es., monitoraggio della temperatura su una vasta area). Tali aspetti caratterizzanti rendono inadeguate le tradizionali metodologie di progetto e test basate sul concetto di architettura gerarchica e incapsulamento delle funzionalita' (modello ISO/OSI). Probabilmente e' proprio la mancanza di metodologie di progetto specifiche per questo tipo di applicazioni che finora ne ha limitato l'adozione nel mondo industriale. D'altro lato proprio tali aspetti caratterizzanti avvicinano la progettazione di tali reti a quella dei sistemi integrati dove sistemi complessi sono creati a partire da un numero elevato di elementi semplici grazie alla presenza di metodi formali e strumenti automatici che hanno alzato il grado di astrazione a cui lavora il progettista. Durante il seminario verranno illustrate in dettaglio le principali sfide tecnologiche del progetto di reti di sistemi embedded ed alcune soluzioni applicate specificatamente al progetto di reti di sensori. Il seminario ha come oggetto la progettazione di applicazioni complesse basate su sistemi embedded di rete. Questo ambito e' oggetto di una straordinaria attenzione da parte della comunita' scientifica e del mondo industriale perche' promette di rivoluzionare il modo di costruire reti di telecomunicazioni e di realizzare la cosiddetta "ambient intelligence". Gli aspetti caratterizzanti delle reti di sistemi embedded sono: 1) presenza di un grande numero di nodi, 2) collaborazione tra i nodi al fine di raggiungere un obiettivo comune indipendente dal singolo nodo (ad es., monitoraggio della temperatura su una vasta area). Tali aspetti caratterizzanti rendono inadeguate le tradizionali metodologie di progetto e test basate sul concetto di architettura gerarchica e incapsulamento delle funzionalita' (modello ISO/OSI). Probabilmente e' proprio la mancanza di metodologie di progetto specifiche per questo tipo di applicazioni che finora ne ha limitato l'adozione nel mondo industriale. D'altro lato proprio tali aspetti caratterizzanti avvicinano la progettazione di tali reti a quella dei sistemi integrati dove sistemi complessi sono creati a partire da un numero elevato di elementi semplici grazie alla presenza di metodi formali e strumenti automatici che hanno alzato il grado di astrazione a cui lavora il progettista. Durante il seminario verranno illustrate in dettaglio le principali sfide tecnologiche del progetto di reti di sistemi embedded ed alcune soluzioni applicate specificatamente al progetto di reti di sensori.